282 lines
8.2 KiB
Zig
282 lines
8.2 KiB
Zig
// SPDX-License-Identifier: LCL-1.0
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// Copyright (c) 2026 Markus Maiwald
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// Stewardship: Self Sovereign Society Foundation
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//
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// This file is part of the Nexus Commonwealth.
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// See legal/LICENSE_COMMONWEALTH.md for license terms.
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//! Rumpk Layer 0: UART Driver
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//!
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//! Minimal serial I/O for QEMU 'virt' machine.
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//! Supports PL011 (ARM64) and 16550A (RISC-V).
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//!
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//! SAFETY: All MMIO accesses use volatile pointers.
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//! Ring buffer is initialized to undefined for performance;
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//! head/tail indices ensure only written bytes are read.
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const std = @import("std");
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const builtin = @import("builtin");
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// ARM64 PL011 Constants
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const PL011_BASE: usize = 0x09000000;
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const PL011_DR: usize = 0x00;
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const PL011_FR: usize = 0x18;
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const PL011_TXFF: u32 = 1 << 5;
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// RISC-V 16550A Constants
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const NS16550A_BASE: usize = 0x10000000;
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const NS16550A_THR: usize = 0x00; // Transmitter Holding Register
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const NS16550A_LSR: usize = 0x05; // Line Status Register
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const NS16550A_THRE: u8 = 1 << 5; // Transmitter Holding Register Empty
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const NS16550A_IER: usize = 0x01; // Interrupt Enable Register
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const NS16550A_FCR: usize = 0x02; // FIFO Control Register
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const NS16550A_LCR: usize = 0x03; // Line Control Register
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// Input Ring Buffer (256 bytes, power of 2 for fast masking)
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const INPUT_BUFFER_SIZE = 256;
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// SAFETY(RingBuffer): Only accessed via head/tail indices.
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// SAFETY(RingBuffer): Only accessed via head/tail indices.
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// Bytes are written before read. No uninitialized reads possible.
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var input_buffer: [INPUT_BUFFER_SIZE]u8 = undefined;
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var input_head = std.atomic.Value(u32).init(0); // Write position
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var input_tail = std.atomic.Value(u32).init(0); // Read position
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pub fn init() void {
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// Initialize buffer pointers
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input_head.store(0, .monotonic);
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input_tail.store(0, .monotonic);
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switch (builtin.cpu.arch) {
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.riscv64 => init_riscv(),
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else => {},
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}
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}
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pub fn init_riscv() void {
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const base = NS16550A_BASE;
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// 1. Enable Interrupts (Received Data Available)
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const ier: *volatile u8 = @ptrFromInt(base + NS16550A_IER);
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ier.* = 0x01; // 0x01 = Data Ready Interrupt.
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// 2. Disable FIFO (16450 Mode) to ensure immediate non-buffered input visibility
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const fcr: *volatile u8 = @ptrFromInt(base + NS16550A_FCR);
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fcr.* = 0x00;
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// 2b. Enable Modem Control (DTR | RTS | OUT2)
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// Essential for allowing interrupts and signaling readiness
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const mcr: *volatile u8 = @ptrFromInt(base + 0x04); // NS16550A_MCR
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mcr.* = 0x0B;
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// 3. Set LCR to 8N1
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const lcr: *volatile u8 = @ptrFromInt(base + NS16550A_LCR);
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lcr.* = 0x03;
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// --- LOOPBACK TEST ---
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// Enable Loopback Mode (Bit 4 of MCR)
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mcr.* = 0x1B; // 0x0B | 0x10
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// Write a test byte: 0xA5
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const thr: *volatile u8 = @ptrFromInt(base + NS16550A_THR);
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const lsr: *volatile u8 = @ptrFromInt(base + NS16550A_LSR);
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// Wait for THRE
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while ((lsr.* & NS16550A_THRE) == 0) {}
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thr.* = 0xA5;
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// Wait for Data Ready
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var timeout: usize = 1000000;
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while ((lsr.* & 0x01) == 0 and timeout > 0) {
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timeout -= 1;
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}
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var passed = false;
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var reason: []const u8 = "Timeout";
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if ((lsr.* & 0x01) != 0) {
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// Read RBR
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const rbr: *volatile u8 = @ptrFromInt(base + 0x00);
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const val = rbr.*;
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if (val == 0xA5) {
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passed = true;
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} else {
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reason = "Data Mismatch";
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}
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}
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// Disable Loopback (Restore MCR)
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mcr.* = 0x0B;
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if (passed) {
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write_bytes("[UART] Loopback Test: PASS\n");
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} else {
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write_bytes("[UART] Loopback Test: FAIL (");
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write_bytes(reason);
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write_bytes(")\n");
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}
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// Capture any data already in hardware FIFO
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poll_input();
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}
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/// Poll UART hardware and move available bytes into ring buffer
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/// Should be called periodically (e.g. from scheduler or ISR)
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pub fn poll_input() void {
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switch (builtin.cpu.arch) {
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.riscv64 => {
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const thr: *volatile u8 = @ptrFromInt(NS16550A_BASE + NS16550A_THR);
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const lsr: *volatile u8 = @ptrFromInt(NS16550A_BASE + NS16550A_LSR);
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// Read all available bytes from UART FIFO
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while ((lsr.* & 0x01) != 0) { // Data Ready
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const byte = thr.*;
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// Add to ring buffer if not full
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const head_val = input_head.load(.monotonic);
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const tail_val = input_tail.load(.monotonic);
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const next_head = (head_val + 1) % INPUT_BUFFER_SIZE;
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if (next_head != tail_val) {
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input_buffer[head_val] = byte;
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input_head.store(next_head, .monotonic);
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}
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// If full, drop the byte (could log this in debug mode)
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}
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},
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.aarch64 => {
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const dr: *volatile u32 = @ptrFromInt(PL011_BASE + PL011_DR);
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const fr: *volatile u32 = @ptrFromInt(PL011_BASE + PL011_FR);
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while ((fr.* & (1 << 4)) == 0) { // RXFE (Receive FIFO Empty) is bit 4
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const byte: u8 = @truncate(dr.*);
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const head_val = input_head.load(.monotonic);
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const tail_val = input_tail.load(.monotonic);
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const next_head = (head_val + 1) % INPUT_BUFFER_SIZE;
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if (next_head != tail_val) {
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input_buffer[head_val] = byte;
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input_head.store(next_head, .monotonic);
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}
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}
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},
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else => {},
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}
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}
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fn write_char_arm64(c: u8) void {
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const dr: *volatile u32 = @ptrFromInt(PL011_BASE + PL011_DR);
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const fr: *volatile u32 = @ptrFromInt(PL011_BASE + PL011_FR);
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while ((fr.* & PL011_TXFF) != 0) {}
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dr.* = c;
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}
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fn write_char_riscv64(c: u8) void {
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const thr: *volatile u8 = @ptrFromInt(NS16550A_BASE + NS16550A_THR);
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const lsr: *volatile u8 = @ptrFromInt(NS16550A_BASE + NS16550A_LSR);
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// Wait for THRE (Transmitter Holding Register Empty)
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while ((lsr.* & NS16550A_THRE) == 0) {}
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thr.* = c;
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}
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fn write_char(c: u8) void {
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switch (builtin.cpu.arch) {
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.aarch64 => write_char_arm64(c),
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.riscv64 => write_char_riscv64(c),
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else => {}, // Do nothing on others
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}
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}
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pub fn write_bytes(bytes: []const u8) void {
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for (bytes) |b| {
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if (b == '\n') {
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write_char('\r');
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}
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write_char(b);
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}
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}
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pub fn read_byte() ?u8 {
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// First, poll UART to refill buffer
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poll_input();
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// Then read from buffer
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const head_val = input_head.load(.monotonic);
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const tail_val = input_tail.load(.monotonic);
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if (tail_val != head_val) {
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const byte = input_buffer[tail_val];
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input_tail.store((tail_val + 1) % INPUT_BUFFER_SIZE, .monotonic);
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return byte;
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}
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return null;
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}
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pub fn read_direct() ?u8 {
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switch (builtin.cpu.arch) {
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.riscv64 => {
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const thr: *volatile u8 = @ptrFromInt(NS16550A_BASE + NS16550A_THR);
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const lsr: *volatile u8 = @ptrFromInt(NS16550A_BASE + NS16550A_LSR);
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if ((lsr.* & 0x01) != 0) {
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return thr.*;
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}
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},
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else => {},
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}
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return null;
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}
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pub fn get_lsr() u8 {
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switch (builtin.cpu.arch) {
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.riscv64 => {
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const lsr: *volatile u8 = @ptrFromInt(NS16550A_BASE + NS16550A_LSR);
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return lsr.*;
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},
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else => return 0,
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}
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}
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pub fn puts(s: []const u8) void {
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write_bytes(s);
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}
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pub fn putc(c: u8) void {
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if (c == '\n') {
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write_char('\r');
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}
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write_char(c);
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}
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pub fn print(s: []const u8) void {
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puts(s);
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}
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pub const Writer = struct {
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pub const Error = error{};
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pub fn write(self: Writer, bytes: []const u8) Error!usize {
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_ = self;
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write_bytes(bytes);
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return bytes.len;
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}
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pub fn print(self: Writer, comptime fmt: []const u8, args: anytype) Error!void {
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return std.fmt.format(self, fmt, args);
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}
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};
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pub fn print_hex(value: usize) void {
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const hex_chars = "0123456789ABCDEF";
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write_bytes("0x");
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var i: usize = 0;
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while (i < 16) : (i += 1) {
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const shift: u6 = @intCast((15 - i) * 4);
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const nibble = (value >> shift) & 0xF;
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write_char(hex_chars[nibble]);
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}
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}
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export fn uart_print_hex(value: u64) void {
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print_hex(value);
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}
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