479 lines
13 KiB
Zig
479 lines
13 KiB
Zig
// SPDX-License-Identifier: LCL-1.0
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// Copyright (c) 2026 Markus Maiwald
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// Stewardship: Self Sovereign Society Foundation
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//
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// This file is part of the Nexus Commonwealth.
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// See legal/LICENSE_COMMONWEALTH.md for license terms.
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//! Rumpk HAL: RISC-V Entry Point (Sovereign Trap Architecture)
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//!
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//! This is the hardware floor for RISC-V64. Sets up stack, trap vectors,
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//! S-mode transition, and memory management before handing off to Nim.
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//!
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//! SAFETY: Runs in bare-metal S-mode with Sv39 paging.
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const std = @import("std");
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const uart = @import("uart.zig");
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const virtio_net = @import("virtio_net.zig");
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// =========================================================
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// Entry Point (Naked)
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// =========================================================
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export fn _start() callconv(.naked) noreturn {
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asm volatile (
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// 1. Disable Interrupts
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\\ csrw sie, zero
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\\ csrw satp, zero
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\\ csrw sscratch, zero
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// 1.1 Enable FPU (sstatus.FS = Initial [01])
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\\ li t0, 0x2000
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\\ csrs sstatus, t0
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// 1.2 Initialize Global Pointer
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\\ .option push
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\\ .option norelax
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\\ la gp, __global_pointer$
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\\ .option pop
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// 1.5 Clear BSS (Zero out uninitialized globals)
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\\ la t0, __bss_start
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\\ la t1, __bss_end
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\\ bge t0, t1, 2f
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\\ 1:
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\\ sb zero, (t0)
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\\ addi t0, t0, 1
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\\ blt t0, t1, 1b
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\\ 2:
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// 2. Set up Stack
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\\ la sp, stack_bytes
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\\ li t0, 65536
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\\ add sp, sp, t0
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// 2.1 Install Trap Handler (Direct Mode)
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\\ la t0, trap_entry
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\\ csrw stvec, t0
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// 3. Jump to Zig Entry
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\\ call zig_entry
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\\ 1: wfi
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\\ j 1b
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);
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unreachable;
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}
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// Trap Frame Layout (Packed on stack)
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const TrapFrame = extern struct {
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ra: usize,
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gp: usize,
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tp: usize,
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t0: usize,
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t1: usize,
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t2: usize,
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s0: usize,
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s1: usize,
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a0: usize,
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a1: usize,
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a2: usize,
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a3: usize,
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a4: usize,
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a5: usize,
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a6: usize,
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a7: usize,
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s2: usize,
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s3: usize,
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s4: usize,
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s5: usize,
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s6: usize,
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s7: usize,
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s8: usize,
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s9: usize,
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s10: usize,
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s11: usize,
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t3: usize,
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t4: usize,
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t5: usize,
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t6: usize,
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sepc: usize,
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sstatus: usize,
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scause: usize,
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stval: usize,
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};
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// Full Context Save Trap Entry
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export fn trap_entry() align(4) callconv(.naked) void {
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asm volatile (
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// 🔧 CRITICAL FIX: Stack Switching (User -> Kernel)
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// Swap sp and sscratch.
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// If from User: sp=KStack, sscratch=UStack
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// If from Kernel: sp=0, sscratch=ValidStack (Problematic logic if not careful)
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// Correct Logic:
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// If sscratch == 0: We came from Kernel. sp is already KStack. Do NOTHING to sp.
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// If sscratch != 0: We came from User. sp is UStack. Swap to get KStack.
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\\ csrrw sp, sscratch, sp
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\\ bnez sp, 1f
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// Kernel -> Kernel (recursive). Restore sp from sscratch (which had the 0).
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\\ csrrw sp, sscratch, sp
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\\ 1:
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// Allocation (36*8 = 288 bytes)
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\\ addi sp, sp, -288
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// Save Registers (GPRs)
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\\ sd ra, 0(sp)
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\\ sd gp, 8(sp)
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\\ sd tp, 16(sp)
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\\ sd t0, 24(sp)
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\\ sd t1, 32(sp)
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\\ sd t2, 40(sp)
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\\ sd s0, 48(sp)
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\\ sd s1, 56(sp)
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\\ sd a0, 64(sp)
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\\ sd a1, 72(sp)
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\\ sd a2, 80(sp)
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\\ sd a3, 88(sp)
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\\ sd a4, 96(sp)
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\\ sd a5, 104(sp)
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\\ sd a6, 112(sp)
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\\ sd a7, 120(sp)
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\\ sd s2, 128(sp)
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\\ sd s3, 136(sp)
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\\ sd s4, 144(sp)
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\\ sd s5, 152(sp)
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\\ sd s6, 160(sp)
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\\ sd s7, 168(sp)
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\\ sd s8, 176(sp)
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\\ sd s9, 184(sp)
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\\ sd s10, 192(sp)
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\\ sd s11, 200(sp)
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\\ sd t3, 208(sp)
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\\ sd t4, 216(sp)
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\\ sd t5, 224(sp)
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\\ sd t6, 232(sp)
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// RELOAD KERNEL GLOBAL POINTER (Critical for globals access)
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\\ .option push
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\\ .option norelax
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\\ la gp, __global_pointer$
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\\ .option pop
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// Save CSRs
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\\ csrr t0, sepc
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\\ sd t0, 240(sp)
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\\ csrr t1, sstatus
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\\ sd t1, 248(sp)
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\\ csrr t2, scause
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\\ sd t2, 256(sp)
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\\ csrr t3, stval
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\\ sd t3, 264(sp)
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// Call Handler (Arg0 = Frame Pointer)
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\\ mv a0, sp
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\\ call rss_trap_handler
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// Restore CSRs (Optional if modified? sepc changed for syscall)
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\\ ld t0, 240(sp)
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\\ csrw sepc, t0
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// sstatus often modified to change mode? For return, we use sret.
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// We might want to restore sstatus if we support nested interrupts properly.
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\\ ld t1, 248(sp)
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\\ csrw sstatus, t1
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// Restore Encapsulated User Context
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\\ ld ra, 0(sp)
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\\ ld gp, 8(sp)
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\\ ld tp, 16(sp)
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\\ ld t0, 24(sp)
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\\ ld t1, 32(sp)
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\\ ld t2, 40(sp)
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\\ ld s0, 48(sp)
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\\ ld s1, 56(sp)
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\\ ld a0, 64(sp)
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\\ ld a1, 72(sp)
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\\ ld a2, 80(sp)
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\\ ld a3, 88(sp)
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\\ ld a4, 96(sp)
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\\ ld a5, 104(sp)
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\\ ld a6, 112(sp)
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\\ ld a7, 120(sp)
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\\ ld s2, 128(sp)
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\\ ld s3, 136(sp)
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\\ ld s4, 144(sp)
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\\ ld s5, 152(sp)
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\\ ld s6, 160(sp)
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\\ ld s7, 168(sp)
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\\ ld s8, 176(sp)
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\\ ld s9, 184(sp)
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\\ ld s10, 192(sp)
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\\ ld s11, 200(sp)
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\\ ld t3, 208(sp)
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\\ ld t4, 216(sp)
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\\ ld t5, 224(sp)
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\\ ld t6, 232(sp)
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// Deallocate stack
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\\ addi sp, sp, 288
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// 🔧 CRITICAL FIX: Swap back sscratch <-> sp ONLY if returning to User Mode
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// Check sstatus.SPP (Bit 8). 0 = User, 1 = Supervisor.
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\\ csrr t0, sstatus
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\\ li t1, 0x100
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\\ and t0, t0, t1
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\\ bnez t0, 2f
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// Returning to User: Swap sp (Kernel Stack) with sscratch (User Stack)
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\\ csrrw sp, sscratch, sp
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\\ 2:
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\\ sret
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);
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}
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// L1 Kernel Logic
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extern fn k_handle_syscall(nr: usize, a0: usize, a1: usize, a2: usize) usize;
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extern fn k_handle_exception(scause: usize, sepc: usize, stval: usize) void;
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extern fn k_check_deferred_yield() void;
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export fn rss_trap_handler(frame: *TrapFrame) void {
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const scause = frame.scause;
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// uart.print("[Trap] Entered Handler. scause: ");
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// uart.print_hex(scause);
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// uart.print("\n");
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// Check high bit: 0 = Exception, 1 = Interrupt
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if ((scause >> 63) != 0) {
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const intr_id = scause & 0x7FFFFFFFFFFFFFFF;
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if (intr_id == 9) {
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// PLIC Context 1 (Supervisor) Claim/Complete Register
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const PLIC_CLAIM: *volatile u32 = @ptrFromInt(0x0c201004);
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const irq = PLIC_CLAIM.*;
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if (irq == 10) { // UART0 is IRQ 10 on Virt machine
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uart.poll_input();
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} else if (irq >= 32 and irq <= 35) {
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virtio_net.virtio_net_poll();
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} else if (irq == 0) {
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// Spurious or no pending interrupt
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}
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// Complete the interrupt
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PLIC_CLAIM.* = irq;
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} else if (intr_id == 5) {
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// Supervisor Timer Interrupt
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// Disable (One-shot)
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asm volatile ("csrc sie, %[mask]"
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:
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: [mask] "r" (@as(usize, 1 << 5)),
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);
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// Call Nim Handler
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rumpk_timer_handler();
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}
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k_check_deferred_yield();
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return;
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}
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// 8: ECALL from U-mode
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// 9: ECALL from S-mode
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if (scause == 8 or scause == 9) {
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// Advance PC to skip 'ecall' instruction (4 bytes)
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frame.sepc += 4;
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// Dispatch Syscall
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const res = k_handle_syscall(frame.a7, frame.a0, frame.a1, frame.a2);
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// Write result back to a0
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frame.a0 = res;
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// DIAGNOSTIC: Syscall completed
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// uart.print("[Trap] Syscall done, returning to userland\n");
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k_check_deferred_yield();
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return;
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}
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// Delegate all other exceptions to the Kernel Immune System
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k_handle_exception(scause, frame.sepc, frame.stval);
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// Safety halt if kernel returns (should be unreachable)
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while (true) {}
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}
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// SAFETY(Stack): Memory is immediately used by _start before any read.
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// Initialized to `undefined` for performance (no zeroing 64KB at boot).
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export var stack_bytes: [64 * 1024]u8 align(16) = undefined;
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const hud = @import("hud.zig");
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extern fn kmain() void;
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extern fn NimMain() void;
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extern fn rumpk_timer_handler() void;
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export fn zig_entry() void {
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uart.init_riscv();
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// 🔧 CRITICAL FIX: Enable SUM (Supervisor User Memory) Access
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// S-mode needs to write to U-mode pages (e.g. loading apps at 0x88000000)
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// sstatus.SUM is bit 18 (0x40000)
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asm volatile (
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\\ li t0, 0x40000
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\\ csrs sstatus, t0
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);
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uart.print("[Rumpk L0] zig_entry reached\n");
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uart.print("[Rumpk RISC-V] Handing off to Nim L1...\n");
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// Networking is initialized by kmain -> rumpk_net_init
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NimMain();
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kmain();
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rumpk_halt();
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}
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export fn console_write(ptr: [*]const u8, len: usize) void {
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uart.write_bytes(ptr[0..len]);
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}
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export fn console_read() c_int {
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if (uart.read_byte()) |b| {
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return @as(c_int, b);
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}
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return -1;
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}
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export fn console_poll() void {
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uart.poll_input();
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}
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export fn debug_uart_lsr() u8 {
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return uart.get_lsr();
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}
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const virtio_block = @import("virtio_block.zig");
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extern fn hal_surface_init() void;
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export fn hal_io_init() void {
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uart.init();
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hal_surface_init();
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// Network init is now called explicitly by kernel (rumpk_net_init)
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virtio_block.init();
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}
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export fn rumpk_halt() noreturn {
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uart.print("[Rumpk RISC-V] Halting.\n");
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while (true) {
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asm volatile ("wfi");
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}
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}
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// RISC-V Time Constants
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const TIMEBASE: u64 = 10_000_000; // QEMU 'virt' machine (10 MHz)
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const SBI_TIME_EID: u64 = 0x54494D45;
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fn rdtime() u64 {
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var ticks: u64 = 0;
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asm volatile ("rdtime %[ticks]"
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: [ticks] "=r" (ticks),
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);
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return ticks;
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}
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fn sbi_set_timer(stime_value: u64) void {
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asm volatile (
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\\ ecall
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:
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: [arg0] "{a0}" (stime_value),
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[eid] "{a7}" (SBI_TIME_EID),
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[fid] "{a6}" (0), // FID 0 = set_timer
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: .{ .memory = true });
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}
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export fn rumpk_timer_now_ns() u64 {
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return rdtime() * 100; // 10MHz = 100ns/tick
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}
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export fn rumpk_timer_set_ns(interval_ns: u64) void {
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if (interval_ns == std.math.maxInt(u64)) {
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sbi_set_timer(std.math.maxInt(u64));
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// Disable STIE
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asm volatile ("csrc sie, %[mask]"
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:
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: [mask] "r" (@as(usize, 1 << 5)),
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);
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return;
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}
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const ticks = interval_ns / 100; // 100ns per tick for 10MHz
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const now = rdtime();
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const next_time = now + ticks;
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sbi_set_timer(next_time);
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// Enable STIE (Supervisor Timer Interrupt Enable)
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asm volatile ("csrs sie, %[mask]"
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:
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: [mask] "r" (@as(usize, 1 << 5)),
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);
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}
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// =========================================================
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// KEXEC (The Phoenix Protocol)
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// =========================================================
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export fn hal_kexec(entry: u64, dtb: u64) noreturn {
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// 1. Disable Interrupts
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asm volatile ("csrc sstatus, 2");
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// 2. Disable MMU (Return to Physical Reality)
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// WARNING: This assumes we are Identity Mapped (VA=PA) or executing from a location
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// where PA is the same. mm.zig creates Identity Map for Kernel code.
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asm volatile ("csrw satp, zero");
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asm volatile ("sfence.vma zero, zero");
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// 3. Jump to new kernel
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asm volatile (
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\\ jr %[entry]
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:
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: [entry] "r" (entry),
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[dtb] "{a1}" (dtb),
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[hart] "{a0}" (0),
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);
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unreachable;
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}
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// =========================================================
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// USERLAND TRANSITION
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// =========================================================
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export fn hal_enter_userland(entry: u64, systable: u64, sp: u64) callconv(.c) void {
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// 1. Set up sstatus: SPP=0 (User), SPIE=1 (Enable interrupts on return)
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// 2. Set sepc to entry point
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// 3. Set sscratch to current kernel stack
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// 4. Transition via sret
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var kstack: usize = 0;
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asm volatile ("mv %[kstack], sp"
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: [kstack] "=r" (kstack),
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);
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asm volatile (
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\\ li t0, 0x20 // sstatus.SPIE = 1 (bit 5)
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\\ csrs sstatus, t0
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\\ li t1, 0x100 // sstatus.SPP = 1 (bit 8)
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\\ csrc sstatus, t1
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\\ li t2, 0x40000 // sstatus.SUM = 1 (bit 18)
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\\ csrs sstatus, t2
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\\ csrw sepc, %[entry]
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\\ csrw sscratch, %[kstack]
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\\ mv sp, %[sp]
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\\ mv a0, %[systable]
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\\ sret
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:
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: [entry] "r" (entry),
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[systable] "r" (systable),
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[sp] "r" (sp),
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[kstack] "r" (kstack),
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);
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}
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