155 lines
4.0 KiB
Zig
155 lines
4.0 KiB
Zig
// MARKUS MAIWALD (ARCHITECT) | VOXIS FORGE (AI)
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// RUMPK HAL // RISC-V ENTRY
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const std = @import("std");
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const uart = @import("uart.zig");
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const virtio_net = @import("virtio_net.zig");
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// =========================================================
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// Entry Point (Naked)
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// =========================================================
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export fn _start() callconv(.naked) noreturn {
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asm volatile (
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// 1. Disable Interrupts
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\\ csrw sie, zero
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\\ csrw satp, zero
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// 1.1 Enable FPU (sstatus.FS = Initial [01])
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\\ li t0, 0x2000
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\\ csrs sstatus, t0
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// 1.2 Initialize Global Pointer
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\\ .option push
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\\ .option norelax
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\\ la gp, __global_pointer$
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\\ .option pop
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// 2. Set up Stack
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\\ la sp, stack_bytes
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\\ li t0, 65536
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\\ add sp, sp, t0
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// 2.1 Install Trap Handler (Direct Mode)
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\\ la t0, trap_entry
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\\ csrw stvec, t0
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// 3. Jump to Zig Entry
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\\ call zig_entry
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\\ 1: wfi
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\\ j 1b
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);
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unreachable;
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}
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export fn trap_entry() callconv(.naked) void {
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asm volatile (
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\\ // Minimal context save (clobbering scratch regs for debug)
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\\ csrr t0, scause
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\\ csrr t1, sepc
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\\ csrr t2, stval
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\\ mv a0, t0
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\\ mv a1, t1
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\\ mv a2, t2
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\\ call rss_trap_handler
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\\ 1: wfi
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\\ j 1b
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);
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}
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export fn rss_trap_handler(cause: usize, epc: usize, val: usize) void {
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uart.print("\n\n!!! SOVEREIGN TRAP !!!\n");
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uart.print("SCAUSE: 0x");
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uart.print_hex(cause);
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uart.print("\n");
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uart.print("SEPC: 0x");
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uart.print_hex(epc);
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uart.print("\n");
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uart.print("STVAL: 0x");
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uart.print_hex(val);
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uart.print("\n");
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uart.print("SYSTEM HALTED.\n");
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while (true) {}
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}
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// =========================================================
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// Stack (64KB)
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// =========================================================
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export var stack_bytes: [64 * 1024]u8 align(16) = undefined;
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const hud = @import("hud.zig");
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// =========================================================
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// Zig Higher-Level Entry
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// =========================================================
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extern fn kmain() void;
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extern fn NimMain() void;
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export fn zig_entry() void {
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// UART init (QEMU default 0x10000000)
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uart.init_riscv();
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uart.print("[Rumpk L0] zig_entry reached\n");
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// HUD DISABLED FOR PHASE 8.7 - LINEAR LOGGING ONLY
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// hud.set_color(36); // Cyan
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// hud.draw_box(1, 1, 80, 3, "RUMPK HUD v0.1");
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// hud.draw_box(1, 4, 80, 20, "NEXSHELL CONSOLE");
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// hud.draw_box(1, 24, 80, 2, "IDENTITY");
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// hud.move_to(2, 4);
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// uart.print("CPU: RISC-V 64 | STATUS: INITIALIZING | MASK: SOVEREIGN");
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// hud.move_to(25, 4);
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// uart.print("CELL: /Cell/Root | ID: 0xDEADBEEF");
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// hud.move_to(5, 4);
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// hud.reset_color();
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uart.print("[Rumpk RISC-V] Handing off to Nim L1...\n");
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// VirtIO Init moved to Kernel L1 (Sovereign Mode)
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_ = virtio_net;
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// Initialize Nim Runtime
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NimMain();
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// Call Kernel
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kmain();
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// Halt if return
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rumpk_halt();
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}
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// =========================================================
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// HAL Exports to Nim (ABI Contract)
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// =========================================================
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export fn console_write(ptr: [*]const u8, len: usize) void {
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uart.write_bytes(ptr[0..len]);
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}
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export fn console_read() c_int {
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if (uart.read_byte()) |b| {
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return @as(c_int, b);
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}
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return -1;
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}
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const virtio_block = @import("virtio_block.zig");
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export fn hal_io_init() void {
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virtio_net.init();
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virtio_block.init();
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}
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export fn rumpk_halt() noreturn {
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uart.print("[Rumpk RISC-V] Halting.\n");
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while (true) {
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asm volatile ("wfi");
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}
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}
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var mock_ticks: u64 = 0;
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export fn rumpk_timer_now_ns() u64 {
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// Phase 1 Mock: Incrementing counter to simulate time passage per call
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// This allows Watchdog logic to detect elapsed "time" in coop loop.
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mock_ticks += 100000; // 100us per call
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return mock_ticks;
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}
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